1. Field of the Invention
The present invention relates generally to systems and methods for employing electronic memory cost effectively in area, process, power and testing, in a microelectronic device. More particularly, the present invention relates to systems and methods for reducing the physical size of a memory used for handling serial data.
2. Related Art
The EVIAC (one of the first electronic computers) filled the size of one room and consumed an enormous amount of power. Today, a computer with similar or better specifications is able to fit in the palm of a human hand, and operate at a very, very low level of power.
The invention of semiconductor devices, particularly integrated circuits, has allowed engineers and scientists to reduce the size and cost of computer devices while increasing their capabilities and reliability.
Storage of data is one of the key requirements of any computer system. The processor of the computer needs to be able to access very quickly and efficiently specific data in a large set of data. For reasons of cost, the large set of data is typically stored hierarchically in a slow speed storage device such as a disk drive. The processor indicates to the disk drive the data it needs through the memory hierarchy.
The disk drive is controlled by a controller which retrieves data from, and stores data to, the disk drive. This data is transferred between the processor and the disk drive via a bus.
The cost and speed of data retrieval and storage are system parameters which have a significant impact on system performance and therefore the computer industry is constantly seeking to improve these parameters. Such is the case with the present invention.
An architectural development to increase speed in disk drives is a data buffer positioned between the slow speed disk drive and the much faster processor. Data is buffered and organized to reduce transfer time to the processor. The present invention contemplates presently known and future developed buffering operations.
FIG. 1 illustrates at an architectural, block, high level a disk controller designated generally by a reference number 101. Disk controller 101 stores and retrieves data upon command. Note that error correction coding (ECC) is some, times used. Disk controller 101 includes a buffer memory 102 (which is typically a static random access memory (SRAM)), a disk drive 104 (or similar input/output storage device, not shown), and a controller 106. Buffer SRAM 102 acts in a conventional manner as a data storage means linking disk drive 104 with the rest of a computer system 120. Computer system 120 can be of any type from a super computer to a computer on a chip to a distributed architecture system. Computer system 120 is not shown, but is labeled: other devices. Controller 106 controls data transfer via commands received from the other devices for retrieving data from, and sending data to, buffer SRAM 102 via address and control signals on lines 108 and 110.
FIG. 2 shows a high level floor plan representation of a typical implementation in a Complementary Metal Oxide Semiconductor (CMOS) chip 201 of a portion of disk controller 101. Disk controller chip 201 has an input/output (I/O) portion 202, a controller portion 204 (which may include ECC), a timing and interface and logic portion 207, and an SRAM portion 206.
As is apparent from the floor plan of FIG. 2, a very significant portion of the real estate of chip 201 is devoted to buffer SRAM 206. Typically today, buffer SRAM 206 accounts for approximately 50% to 80% of the total area (real estate) allocated on chip 201. As a result, disk controller chip 201 having a buffer SRAM 206 of any significant storage capability requires a large die using presently available CMOS feature sizes and fabrication processes (i.e., single poly, double metal). For example, disk controller chip 201 with 32K byte (256K bits) of memory is limited to a smallest possible die size of approximately 15 mm.times.15 mm (600 mil.sup.2) using 0.8 micron minimum feature size CMOS technology and using at conventional six transistor cell for each bit of buffer SRAM 206.
As is well known, SRAM in CMOS requires a significant number of active devices along with associated overhead devoted to addressing and control. This type of SRAM cell (for storing a single bit of data) needs these active devices and overhead in order to provide random access (read and write) to buffer SRAM 206.
FIGS. 3A and 3B show conventional SRAM cells for storing each bit of data in buffer SRAM 206.
FIG. 3A is a conventional four transistor SRAM cell 300, which is widely used. SRAM cell 300 includes four N-channel devices 302, 304, 306, and 308, and two poly load resistors 310 and 312. It should be noted that the expression "poly load resistor" is a well recognized expression in this field and refers to load resistors formed of high resistivity polycrystalline silicon. Poly load resistors require many additional process steps over a conventional CMOS process. Even using advanced fabrication technology, which is more expensive, a large amount of real estate is required for an SRAM array made up of SRAM cells 300.
FIG. 3B is a conventional six transistor SRAM cell 320. SRAM cell 320 includes two p-channel devices 322 and 324, and four n-channel devices 326, 328, 330 and 332. Each SRAM cell 320 using conventional fabrication technology takes up even more area than the four transistor SRAM cell of FIG. 3A.
What is needed is a buffer memory and a method of buffering data that utilizes conventional CMOS process technology and is capable of being reduced in layout area by a significant amount. In other words, what is needed is a buffer means that is able to utilize conventional CMOS circuit techniques, but which requires less area for the buffer memory function.